Real-time digital spectrum analyzer utilizing the fast fourier transform

ABSTRACT

A digital signal processing system for computing the finite discrete Fourier transform coefficients from a number (N) of digitized samples of an input signal in real time. The signal being analyzed is sampled a predetermined number of times over a given interval, and this number of samples is expressed as the product of two integers, N r1. r2. An array of delay registers is arranged in the form of a matrix having r1columns and r2 rows. The delay registers are controlled so that the contents may be transferred either in a column shift mode or in a row shift mode. While shifting the contents of the array in the row shift mode, the system computes an intermediate set of spectrum estimates which are stored in the array. From this intermediate set, the final coefficients are generated while shifting the contents of the array in its column shift mode.

/T' XR 365736646 [72] Inventor Glenn D. Bel-gland OTHER REFERENCESMorristown, NJ. C0016 & T k A 1 y u ey n gorrthm For the Machme Calculall PP 643,902 tion of Complex Fourier Series Math. of Comp. Vol. 19 pp.[22] Filed June 6, 1967 297 301 April 19 Patented Apr. 6, 1971 T. G.Stockham High Speed Convolution and Correlal 1 Asslgnee s E Researchtion 1966 Spring Joint Computer Conference pp. 229- 233 i 23: Gentleman& Sarde Fast Fourier Transforms For Fun and Profit Fall Joint ComputerConference 1966 pp. 563 78 Primary Examiner-Malcolm A. MorrisonAssistant ExaminerDavid H. Malzahn Attorney-Dawson, Tilton, Fallon andLungmus [54] REAL-TIME DIGITAL SPECTRUM ANALYZER UTILIZING THE FASTFOURIER TRANSFORM ABSTRACT A digital signal processing system forcomputing 5 Claims, 2 Drawing Figs. the finite discrete Fouriertransforrn coefi'rcrents from a number (N) of digitized samples of aninput srgnal in real time.

[52] US. Cl 235/156, The signal being analyzed is sampled apredetermined number of times over a given interval, and this number ofsamples is [51] Int. Cl G06f 7/38 expressed as the product of twointegers, N=r r An array of Field of Search 235/ 156,

delay registers is arranged in the form of a matrix having 324/77 rcolumns and r rows. The delay registers are controlled so that thecontents may be transferred either in a column shift mode or in a rowshift mode. While shifting the contents of the [56] References Citedarray in the row shift mode, the system computes an inter- UNTTED STATESPATENTS mediate set of spectrum estimates which are stored in the ar-3,180,445 4/1965 Schwartz et a1 181/.5 ray. From this intermediate set,the final coefficients are 3,023,966 3/1962 Cox et al 235/81 generatedwhile shifting the contents of the array in its column 3,009,106 11/1961Haase 324/77 shift mode.

1- COLUMNS Ta. l'gb T21;

1 i F DELAY l DELAY I DELAY F REGISTER l REGISTER REGISTER l I A l l l Il i l 6 6 m l l l l I l I 3 1 l I l I .L l

1 r g DELAY 2b DELAY 2 DELAY w REGISTER I REGISTER REGISTER I F l I l al l l I 0 111-1 1 11,. In

DELAY DELAY DELAY REGISTER I aeels'rea i REGISTER l l n -.l L l .1 7 wTen 22 2:! 17

CONTROL 1O 11 13 INPUT vl 2 osueanoaH mar 1 -ff- =SERIAL TRANSFER OFCONTROL SIGNALS ALL OTHER L|NES= PARALLEL TRANSFER OF DATA SIGNALSPatented April 6, 1971 3,573,446

TI COLUMNS --'fi T T2 T] I I I I DELAY DELAY I DELAY REGISTER I REGISTERI REGISTER I A I A I I A I II I I I I o I u I; l I I I I I I I o 211 I I212 I l 271 l DELAY DELAY I DELAY ,2 V REeIs'rER REGISTER REGISTER I l II I I I I I l l 10- I I m I I 117-1 I I DELAY I DELAY DELAY I r I 0 o cI' REGISTER I REGISTER I REGISTER A b L L-- ---J SWITCH l I 21/ 20SWITCH 4 I 17 I 15 'R' REGISTER COMPLE ADDER 15 0 1. w

' GATE SWITCHL PUT j2 COMPLEX 1'1 I 1', J

MLLTIPLIER CONTROL i0 .11 I \2 I UNIT 1g INPUT 7 swrrcn =sERIAL TRANSFEROF CONTROL SIGNALS ALL OTHER L|NES= PARALLEL TRANSFER OF DATA SIGNALSOUTPUT I I r 27 30 3 I I w 21 P REeIsTER awITcII 33 SWITCH COMPLEX 232 XMULTIPLIER 3!! FROM saw j FROM 0 REGISTER 29 CONTROL FROM UNIT [4CONTROL 9' 2 UNIT I4 I flweuo'r' flint 11d REAL-TIME DIGITAL SPECTRUMANALYZER UTILIZING THE FAST FOURIER TRANSFORM BACKGROUND This inventionrelates to a digital signal processing system for computing the finite,discrete Fourier transform coefficients from a given number of samplesof an arbitrary input signal taken over a predetermined time period.

The invention is particularly useful in signal processing apparatus forestimating the frequency spectrum of electrical signals such as might beobtained from sonar echo returns or seismic signals, or other phenomenawherein signal periods can be separated by dead periods in which noinput signal is present. The present invention may also be used inapplications wherein it is necessary to determine the frequency contentof signals as an intermediate step in a more extensive computation. Suchapplications include voice encoding systems, cross correlators, anddigital filters.

Although in many cases spectrum analysis can be performed off line in ageneral-purpose digital computer, other applications require that theestimates of the frequency spectrum be computed in real-time (that is,the computation of the spectrum is effected while the input signal isbeing received). Previous real-time spectrum analyzers have relied upona bank of band-pass filters, each tuned to a separate discrete range ofthe frequency spectrum of interest. Other attempts have suggested usinga single filter which operates sequentially on recurring time-compressedversions of the signal. This single filter could be tuned across thefrequency spectrum, but more often the original signal is mixed with alocal oscillator and swept by a fixed-frequency filter.

In some applications, the input signal varies so slowly that it can besampled, and the spectrum estimates can be computed on a general purposedigital computer in real-time. In most cases, however, the volume of therequired computation and the cost of using a general purpose computerhave rendered these systems impractical from an economical standpoint.

Recently, a new approach was suggested by J. W. Cooley and .l. W. Tukeyin an article which appeared at page 297 of volume 19 Mathematics ofComputation (1965). Their idea eliminated many of the redundantcalculations inherent in prior systems for the evaluation of complexFourier series; however, the idea as disclosed, contemplated performingthe calculations on a general-purpose digital computer thereby renderingspectrum analysis in real-time uneconomical.

SUMMARY The instant invention provides a special purpose digital signalprocessor which can economically perform real-time spectrum analysis asbroadly outlined by Cooley and Tukey. In addition, the present inventioncan be time shared for calculating in real-time the complex Fouriercoefiicients of one or more signals received simultaneously.

THEORY Theoretical aspects of spectrum analysis which will lead to abetter understanding of the instant invention will be discussed before adetailed description of the preferred embodiment is given. For purposesof illustration, it will be assumed that a speech signal has beentransmitted through a low-pass filter so that it contains frequencycomponents only in the range of from zero to 4,000 Hz.

In the analysis, an estimate of the frequency components present in thevoice signal will be obtained by analyzing the periodic repetition of aninterval of the signal lasting for T seconds. That is, a Fourier seriesanalysis will be performed on a periodic function A(t) which isidentical to the function representing the speech signal over somefinite time interval (0,7). The result from a Fourier series analysis ofsuccessive intervals lasting for Tseconds may then serve as an estimateof the spectrum of the speech signal as a function of time.

The Fourier series representation for each A(t) is then given y Eachfunction is the Fourier transform of the other. After being sampled,A(t) can be expressed as where N is the number of samples, T=NAT=thelength of the record, k=0,l, N-l, and AT is the sample period.Therefore,

1 T T (1)= f -[gAmaTwu-kam} W0 Note that w =21r/T=21r/NAT and denoteA(kAT) by Afk). Then In brief, the Cooley and Tukey paper suggests usingcalculations performed in finding one spectral estimate to computeanother spectral estimate. This is done by generating first a set of Nintermediate results and then computing the N spectral estimates fromthese intermediate results.

Thus instead of evaluating equation (8) directly, the following sets ofequations may be evaluated.

Note that by expressing j and k in terms of two other integers,equations (9) and (ID) are fonned and the relabeling of equation I I) isrequired.

The A,terms of equation (9) are the intennediate results which areformed. By making use of each of these intermediate results whilecomputing r different values of A (which are simply relabeled to formthe complex spectral estimates), the total computation required isreduced significantly.

THE DRAWING FIG. 1 is a block schematic diagram of a system according tothe present invention; and

FIG. 2 is a block schematic diagram of apparatus for generating therequired weighting factors in FIG. 1.

DETAILED DESCRIPTION As has already been mentioned, the presentinvention contemplates expressing the number of samples (N) of the inputsignal being analyzed as the product of two integers r and r Referringto FIG. 1, the input samples are received in digitized form at 10 over apredetermined period of time, after which there would be a dead time.The input line 10 (actually a number of parallel lines) is coupled toone signal input of a switch 11. The output of switch 11 is fed to oneinput of a complex multiplier 12. The other input of complex multiplier12 is received from a weighting function generator, hereinafter referredto as a Wgenerator 13 which is illustrated in block schematic form inFIG. 2 and described in detail below.

Switch 11, as well as all of the other functional logic blocksillustrated in this embodiment, may be any of a number of well knowndesigns employing conventional circuitry; and it will not, therefore, bedescribed at the circuit element level, but rather at its functionallevel. The switch 11 has two signal inputs which are received along thehorizontal in FIG. 1, a control input received along the vertical inFIG. 1, and an output line. Again, the single lines represent signalpaths for parallel lines. The control signal is a digital signal whichcouples one of the input signal lines to the output line if the controlsignal is in a first binary state, and it couples the second input lineto the output if the control signal is in a second binary state.

The complex multiplier 12 is a combination of standard binary numbermultipliers which has at its input two complex numbers in binaryrepresentation, each complex number containing a real and an imaginarypart. The complex multiplier 12 generates at its output a complex numberwhich is the product of the two complex numbers at its inputs.

The output of the complex multiplier 12 feeds one input of a complexadder 15. The other input to complex adder 15 is received from a switch16. The complex adder 15 is also a conventional system component indigital processing apparatus, and it generates at its output a complexnumber which is the algebraic sum of the two complex numbers at itbinputs.

The control signal to switch 11 is received from a control unit 14. Thecontrol unit 14 timing information is synchronized with the analog todigital converter which forms the digitalized samples received at input10.

The switch 16 is similar to the switch 11. One of its signal inputs isreceived from an R register, identified by reference numeral 17 in thedrawing. Its control input is received from the control unit 14. The Rregister is a conventional storage register (one flip-flop for eachbinary digit of the number being stored) which will store a complexnumber until a new number is written into it. The R register 17 may beset to zero when a reset command is received from the control unit 14.

The output of R register 17 is also coupled to the input of a gate 18;and the output of the gate 18 is the output of the system, that is, thecomplex spectral estimates generated by the apparatus of FIG. 1. Thegate 18 is also controlled by the control unit 14.

The output of the complex adder I5 is coupled to the input of a switch20 which is controlled by the control unit 14. The switch 20 has onlyone input path, but it has two possible output paths. One output of theswitch 20 is connected to the input of the R register 17; and the otheroutput of the switch 20 is connected to the input of a switch 21. Theswitch 21 is similar to the switch 11; and it, too, is controlled bycontrol unit 14.

The output of the switch 21 is coupled to the input of a memory arraywhich is enclosed in chain line and identified by reference numeral 22.The array 22 includes a total of N (the number of input samples) delayregisters arranged in a matrix having r columns and r rows. Each delayregister is a set of flip-flop circuits capable of storing one complexnumber in binary form together with gating circuitry for receiving inputsignals from either of two sources. The gating or shifting is controlledby the control unit 14.

In describing the interconnections between the various delay registersin the array 22, a convention will be made. In referring to the columnsof the array, the delay registers will be assumed to be arranged inascending order from left to right in FIG. 1; when referring to the rowsof the array, it will be assumed that the delay registers are arrangedin ascending order from bottom to top. Hence, the delay registers of thefirst row are labeled 111, lb, Ir The delay registers of the second roware labeled 2a, 2b, Zn. The delay registers of the highest-order row arelabeled r a, r b, r r

As illustrated by the solid line in the array 22, the delay registersare interconnected such that information from a given register may beshifted upon command to the adjacent register in the next higher ordercolumn, that is, the delay register to its right in FIG. 1. Theinformation in the delay registers of the highest order column, that is,column r is shifted to the input of the delay registers in the nexthigher order row and in the first column. This is illustrated by theinterconnection between the output of delay register lr and the input ofdelay register 2a. These interconnections and this mode of shifting willbe hereafter referred to as row shifting, since the information is firstshifted through one row completely, and then through the next higherorder row until it is shifted through all of the r rows.

A second mode of shifting of information between delay registers in thearray 22 is illustrated in dashed line, and it will hereinafter bereferred to as column shifting. In this mode of shifting, information isshifted between adjacent delay registers in a given column in ascendingrow order; and from the delay register of the highest order row in onecolumn to the delay register of the lowest order row in the column ofnext highest order. This is illustrated by the dashed lineinterconnecting the output of delay register r a and the input of delayregister 1b.

The output from the array 22 (whether information is being transferredin the column shift mode or the row shift mode) is coupled to threeseparate places. The first location to which this information is coupledis a signal input of switch 21; the second place is a signal input ofswitch 16; and the third place is a signal input of switch 11. It willalso be noted that each of the registers in the delay registers may beset to store the number (H-iO when it receives a reset pulse from thecontrol unit 14. In all other cases, the information stored in the delayregisters is received either from a delay register of the next lowerorder row (when the array is in the column shift mode) or from the delayregister in the next lower order column (when the array is in the rowshift mode), except for the end shifts that have previously beenexplained. The delay register 1a of the lowest order row and lowestorder column receives its information from the complex adder 15 throughswitches 20 and 21 or in the alternative from the delay register r r ofthe highest order row and highest order column through switch 21.

The operation of the array is similar to the operation of a conventionaltwo-dimensional shift register where the complex numbers are shifted ateach clock cycle. A preferred implementation of this apparatus employsJK flip-flops as the individual storage elements for each bit in each ofthe delay registers. As is commonly known, these flip-flops perform therequired shifting operations very conveniently. Conventional logic gatescontrol the transmission path to be taken by the string of complexnumbers.

In FIG. 2 is shown in functional block form, the elements required togenerate successive values of W, which is a complex number constitutingan exponential weighting factor, the function of which will be madeclear below. As shown in FIG. 2, a three-state switch 27 has threesignal inputs; the first is received from a block 28 labeled W A secondinput is received from a block 29 labeled W. The values of the lattertwo generators 28 and 29 are simply constant signals which have beenpreset by any conventional means but they are representative of theweighting factors identified in the blocks. The output of switch 27 isconnected to one input of a complex multiplier 30 which is identical infunction to the previously-described complex multiplier 12. The outputof complex multiplier 30 is coupled to the input of a switch 31 which issimilar to the previously-described switch 20.

One of the outputs of the switch 31 is coupled to the input of a Preg'ster 32 which feeds the input of a switch 33, similar to switch 31.The other output of the switch 34 is coupled to the input of a Qregister which feeds the other input of the complex multiplier 30.

One of the outputs of the switch 33 is coupled to the third input of theswitch 27; and the other output of the switch 33 (labeled OUTPUT in FIG.2) is coupled to the input of the complex multiplier 12 in FIG. 1.

The P register 32 and the Q register 34 are conventional flip-flopregisters with one flip-flop for each binary digit stored. When the Pregister receives a reset signal, it is set to the complex number H-iO.When the Q register receives a reset signal, it is set to a complexnumber which corresponds to the complex exponential weighting factor WFor large values of N, further complex exponential weighting factorsmight have to be reset into these registers, but this depends upon thenumber of binary digits carried through the computation and the accuracyrequired in the spectral estimates.

The complex exponential rating factors W and W are required as possibleinputs for complex multiplier 30; and, again depending upon the value ofN and the required accuracy, values of Wwhich can be computed from W andW still might be required to be supplied to halt the accumulation ofround-off errors. I

OPERATION As each complex number A(k) is received at the input of asystem, the following five operations are performed:

1. A(k) is multiplied by the value of W provided by the W generator 13in the complex multiplier 12 of FIG. 1.

2. The contents of the delay registers comprising the array 22 areshifted once in the row shift mode.

3. The information stored in the delay register r r is coupled throughswitch 16 into one input of the complex adder which adds this signalwith the output of the complex multiplier 12.

4. The resulting output of a complex adder 15 is transmitted throughswitches and 21 and stored in delay register la.

5. The same sequential operation defined by steps l4 is repeated untilit has been performed a total of r times.

It will be noted that for the above operation, the switch 11 has beenset such that it will transmit the signal from input 10 to the complexmultiplier 12. At the same time, switch 16 has been set to transmitinformation from the output of the array 22, and switches 20 and 21 havebeen set to transmit information from the complex adder to delayregister la. The delay registers 22 were all set to zero before thefirst multiplication was performed. The gate 18 has been inhibited bycontrol unit 14 so that no signal is transmitted to the output.

A predetermined value of W is required for each of the multiplicationsof step ('1). For each of the first N multiplications,

the same value of W is required, but this is not the case in general.The five operations outlined above are repeated for each of the Ndifferent values of A(k) received at the input. At the end of thiscomplete operation, there have been performed a total number of complexmultiplications equal to the product of N1 thereby requiring a totalnumber of values of W equal to N-r supplied from the W generator 13. Atthe end of this time, the values of A,(k) defined by equation (9), havebeen generated and are stored in the array 22. As has been pointed out,these are the intermediate spectral estimates.

To compute the A values which are the final spectral estimates definedby equation (10), switch 11 is set to transmit the output signals fromthe array 22 to the input of the complex multiplier 12, switch 20 is setto transmit the output of the complex adder 15 to the input of the Rregister 17, and switch 16 is set to transmit the output of the Rregister 17 to the other input of the complex adder 15. At the sametime, switch 21 is set to receive information from the array 22 and theoutput gate 18 is still inhibited. With the system thus set up, thefollowing operations are performed:

1. The R register 17 is reset.

2. The information stored in delay register r r (that is the value ofA,(k) which had been generated) is coupled through switch 11 to thecomplex multiplier 12 which receives at its other input a value from theW generator 13. At this time, the W generator 13 is operating in itssecond mode under direction of control unit 14 as will be describedbelow. The two inputs are then multiplied in the complex multiplier 12.

3. The contents of the R register 17 are coupled through switch 16 andadded to the output of the complex multiplier 12 in the complex adderl5.

4. The output of the complex adder 15 is then shifted through switch 20to the R register 17.

5. The contents of the delay register r r are coupled through switch 21to the input of the delay register 1a. At this time, the array has beenactuated in its column shift mode; and the contents of each of the delayregisters in the array 22 are shifted in this manner.

6. The operation of steps (2), (3), (4), and (5) is repeated for a totalof r times.

7. Gate 18 is then enabled by control unit 14 to transmit the value of acomplex spectral estimate to the output.

8. The operation of steps 1-7 is repeated for a total of N times therebycomputing all N of the complex spectral estimates.

It will be obvious in the second mode of operation, for all of the totalof N times the first 7 operations are performed, a train of r values ofW must be supplied by the W generator 13. Thus, for each spectrumanalysis of N points, a string of N-r values of W must be calculated inthe first mode of operation; and a train of N-r values of W must becalculated in the second mode of operation. This requires that one valuemust be supplied as a multiplier for each of the N(r +r multiplicationsperformed by complex multiplier 12.

OPERATION OF THE WEIGI-ITING FUNCTION GENERATOR The operation of the Wgenerator illustrated in block schematic form in FIG. 2 is as follows.

1. The Q register 34 is reset to a value W 2. The P register 35 is resetto a value W".

3. The contents of the Q register 34 is multiplied by the value of Wcoupled through switch 27 into the complex mul= tiplier 30. The resultis then coupled from the output of the complex multiplier 30 throughswitch 31 back into the Q register 34.

4. The contents of P register 32 are coupled through switch 33 to theinput of the complex multiplier 12 in FIG. 1.

5. Switch 27 is set to its first position, and the contents of the Pregister 32 are multiplied by the contents of the Q register 34 in thecomplex multiplier 30, and the product is stored in the P register 32.

supply the N-r values of W required for the first mode of.

operation of the apparatus of FIG. 1.

The second mode of operation of the W generator 13 will supply the Ntimes r values of W required for its second mode of operation. Thesecond mode of operation is as follows:

1. The Q register 34 is reset to the value of W 2. The P register 32 isreset to a value of W".

3. Switch 27 is set to its third position and the contents of the Qregister 34 are multiplied by the value in the block 29 equal to W. Theresult is then coupled from the output of the complex multiplier 30through switch 31 back into the Q resister 34.

4. The state of switch 33 is changed, and the contents of the P register32 are transmitted to the complex multiplier 12 in FlG. 1.

5. The state of switch 33 is again changed, switch 27 is set to position1, and switch 31 is set to feed the input of the P register 32. Thecontents of the P register 32 are multiplied by the contents of the Qregister 34 in the complex multiplier 30 and the product is stored inthe P register 32.

6. The operation of steps 4 and is repeated for a total of r times.

7. The operation of steps 2-6 is repeated for a total of N times, andthe W register is then reset to its first mode of operation.

I claim:

1. A digital spectrum analyzer for computing the finite discrete Fouriertransform coefficients from a number (N) of digitized samples,represented by A(k), of an input signal comprising: an array of delayregisters forming a matrix having r columns and r rows; row shift meansfor transferring the contents of said delay registers in a row shiftmode wherein the contents of a delay register are transferred to theadjacent register in a higher order column along the same row, thecontents of the delay register in the highest order columns beingtransferred to the delay register in the next higher order row and ofthe lowest order column; means operative independently of said row shiftmeans for transferring the contents of said delay registers in a columnshift mode wherein the contents of said delay registers are transferredalong the same column to an adjacent delay register of higher order row,the contents of the delay registers in the highest order row beingtransferred to the delay register in the next higher order column andlowest order row, the output of the delay register in the highest ordercolumn and highest order row defining the output of said array;multiplier means receiving said input signals for multiplying saidsignal by a predetermined value of a weighting factor; adder means foradding the output of said array and for storing the resultant in thedelay register of lowest order column and lowest order row; and controlmeans for operating on each of said A(k) input signals, said operationincluding transferring said input signal to said multiplier meanswherein it is multiplied by said weighting factor signal, shifting thecontents of said array in said row shift mode, transferring the outputof said multiplier means and the output of said array to said addermeans wherein they are added, and storing the output of said adder meansin the first delay register of said array, said control means operatingon each of said A(k) input signals a total of r times, wherebyintermediate estimates of said Fourier coefficients are stored in saiddelay registers.

2. The apparatus of claim 1 wherein said control means is operativeafter said r, operations to transfer the output of said array to theinput of said multiplier means, and further comprising first registermeans receiving the output signals of said adder means; means forcoupling the output signals of said first register means to one input ofsaid adder means; means for rendering said weighting factor signalgenerator in a second mode of operation for supplying signals to theother input of said complex multiplier; and second control means forrendering operative said multiplier means to multiply the contents ofsaid weighing factor signal generator with the output signals of saidarray, for adding in said adder means the contents of said multipliermeans with the contents of said first register means and for storing theresults in said first register, and for coupling said array output tosaid array input; and means for actuating said array in said columnshift mode and for repeating the operation of said second control meansa total of r times thereby computing each of N of the complex spectralcoefficients which may be fed to an output while operating said array insaid column shift mode.

3. The apparatus of claim 2 wherein said weighting factor signalgenerator comprises: means for storing a constant signal representativeof a value W, means for storing a constant signal representative of avalue W, second multiplier means; second and third register means; meansfor selectively coupling the output of said second multiplier means toeither of said last-named registers; switching means for selectivelycoupling the output signal of said second register to said firstmultiplier means or to said second multiplier means; means forselectively coupling said constant signals to said second multipliermeans; means for setting said third register to a signal valueW meansfor setting said second register to a signal value W; means for couplingthe output of said third register and the output of said signal W" tosaid second multiplier means and for storing the product in said thirdregister; means for coupling the output of said second register to theinput of said first multiplier means as one of said weighting factorsignals; means for selectively coupling the contents of said second andthird registers to the input of said second multiplier means and forstoring the product in said second register; and further control meansfor repeating said last-named operation a total of N times therebysupplying said first N values of said weighting factor signal.

4. The apparatus of claim 3 further comprising means for repeating theoperation therein a total of r times thereby supplying a number N'r ofvalues of said weighting factor required for said first mode ofoperation.

5. The apparatus of claim 4 wherein said means for operating saidweighting factor signal generator in a second mode of operationcomprises means for resetting said third register to a value of W meansfor resetting said second register to a value W means for coupling thecontents of said third register and the contents of said W to saidsecond multiplier; and means for storing the product in said thirdregister; means for selectively coupling the contents of said secondregister to said first multiplier; means whereby the contents of saidsecond and third registers are multiplied and the product stored in saidsecond register; means for repeating said last-named steps a total of rtimes; and means for repeating said second mode of operation a total ofN times thereby supplying a total of N-r values of said weighting factorin said second mode of operatron.

1. A digital spectrum analyzer for computing the finite discrete Fourier transform coefficients from a number (N) of digitized samples, represented by A(k), of an input signal comprising: an array of delay registers forming a matrix having r1 columns and r2 rows; row shift means for transferring the contents of said delay registers in a row shift mode wherein the contents of a delay register are transferred to the adjacent register in a higher order column along the same row, the contents of the delay register in the highest order columns being transferred to the delay register in the next higher order row and of the lowest order column; means operative independently of said row shift means for transferring the contents of said delay registers in a column shift mode wherein the contents of said delay registers are transferred along the same column to an adjacent delay register of higher order row, the contents of the delay registers in the highest order row being transferred to the delay register in the next higher order column and lowest order row, the output of the delay register in the highest order column and highest order row defining the output of said array; multiplier means receiving said input signals for multiplying said signal by a predetermined value of a weighting factor; adder means for adding the output of said array and for storing the resultant in the delay register of lowest order column and lowest order row; and control means for operating on each of said A(k) input signals, said operation including transferring said input signal to said multiplier means wherein it is multiplied by said weighting factor signal, shifting the contents of said array in said row shift mode, transferring the output of said multiplier means and the output of said array to said adder means wherein they are added, and storing the output of said adder means in the first delay register of said array, said control means operating on each of said A(k) input signals a total of r1 times, whereby intermediate estimates of said Fourier coefficients are stored in said delay registers.
 2. The apparatus of claim 1 wherein said control means is operative after said r1 operations to transfer the output of said array to the input of said multiplier means, and further comprising first register means receiving the output signals of said adder means; means for coupling the output signals of said first register means to one input of said adder means; means for rendering said weighting factor signal generator in a second mode of operation for supplying signals to the other input of said complex multiplier; and second control means for rendering operative said multiplier means to multiply the contents of said weighing factor signal generator with the output signals of said array, for adding in said adder means the contents of said multiplier means with the contents of said first register means and for storing the results in said first register, and for coupling said array output to said array input; and means for actuating said array in said column shift mode and for repeating the operation of said second control means a total of r2 times thereby computing each of N of the complex spectral coefficients which may be fed to an output while operating said array in said column shift mode.
 3. The apparatus of claim 2 wherein said weighting factor signal generator comprises: means for storing a constant signal representative of a value Wr ; means for storing a constant signal representative of a value W1, second multiplier means; second and third register means; means for selectively coupling the output of said second multiplier means to either of said last-named registers; switching means for selectively coupling the output signal of said second register to said first multiplier means or to said second multiplier means; means for selectively coupling said constant signals to said second multiplier means; means for setting said third register to a signal value WN r ; means for setting said second register to a signal value W0; means for coupling the output of said third register and the output of said signal Wr to said second multiplier means and for storing the product in said third register; means for coupling the output of said second register to the input of said first multiplier means as one of said weighting factor signals; means for selectively coupling the contents of said second and third registers to the input of said second multiplier means and for storing the product in said second register; and further control means for repeating said last-named operation a total of N times thereby supplying said first N values of said weighting factor signal.
 4. The apparatus of claim 3 further comprising means for repeating the operation therein a total of r1 times thereby supplying a number N.r1 of values of said weighting factor required for said first mode of operation.
 5. The apparatus of claim 4 wherein said means for operating said Weighting factor signal generator in a second mode of operation comprises means for resetting said third register to a value of WN 1; means for resetting said second register to a value W0; means for coupling the contents of said third register and the contents of said W1 to said second multiplier; and means for storing the product in said third register; means for selectively coupling the contents of said second register to said first multiplier; means whereby the contents of said second and third registers are multiplied and the product stored in said second register; means for repeating said last-named steps a total of r2 times; and means for repeating said second mode of operation a total of N times thereby supplying a total of N.r2 values of said weighting factor in said second mode of operation. 